Lower IC Package Structure for Coupling with an Upper IC Package to Form a Package-On-Package (PoP) Assembly and PoP Assembly Including Such a Lower IC Package Structure

ABSTRACT

Disclosed are embodiments of a lower integrated circuit (IC) package structure for a package-on-package (PoP) assembly. The lower IC package structure includes an interposer having pads to mate with terminals of an upper IC package. An encapsulant material is disposed in the lower IC package, and this encapsulant may be disposed proximate one or more IC die. An upper IC package may be coupled with the lower IC package to form a PoP assembly. Such a PoP assembly may be disposed on a mainboard or other circuit board, and may form part of a computing system. Other embodiments are described and claimed.

FIELD OF THE INVENTION

The disclosed embodiments relate generally to integated circuit devices,and more particularly to stacking of integrated circuit packages.

BACKGROUND OF THE INVENTION

Integrated circuit (IC) devices having a small form factor may be usefulin many types of computing systems, such as cell phones, smart phones,tablet computers, electronic reading devices, netbook computers, andlaptop computers, as well as other hand-held or mobile computingsystems. One solution to achieve a small form factor IC device is to usea package-on-package (PoP) architecture, which generally includes anupper IC package stacked over and electrically coupled with a lower ICpackage. The lower IC package may include one or more IC die—and perhapsone or more additional components—disposed on a first substrate or otherdie carrier. Similarly, the upper IC package may include one or more ICdie (and perhaps one or more other components) disposed on a secondsubstrate. In some circumstances, the lower IC package may be fabricatedat one manufacturing facility and the upper IC package fabricated atanother manufacturing facility, and then these two IC packages will needto be mechanically and electrically joined together. The lower ICpackage is electrically coupled to the upper IC package by one or moreinterconnects, and these interconnects may also provide a mechanicalcoupling between these two IC packages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram illustrating a top view of an embodimentof a lower IC package structure.

FIG. 1B is a schematic diagram illustrating a cross-sectional elevationview of the lower IC package of FIG. 1A, as taken along line B-B of FIG.1A.

FIG. 1C is a schematic diagram illustrating a top view of anotherembodiment of a lower IC package structure.

FIG. 1D is a schematic diagram illustrating a cross-sectional elevationview of a further embodiment a lower IC package structure.

FIG. 1E is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 1F is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 1G is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 1H is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 1I is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 1J is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 1K is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 1L is a schematic diagram illustrating a cross-sectional elevationview of another embodiment a lower IC package structure.

FIG. 2A is a schematic diagram illustrating a partial cross-sectionalelevation view of an embodiment a lower IC package including a flowbarrier.

FIG. 2B is a schematic diagram illustrating a partial cross-sectionalelevation view of another embodiment a lower IC package including a flowbarrier.

FIG. 2C is a schematic diagram illustrating a partial cross-sectionalelevation view of a further embodiment a lower IC package including aflow barrier.

FIG. 2D is a schematic diagram illustrating a top view of yet anotherembodiment a lower IC package including a flow barrier.

FIG. 2E is a schematic diagram illustrating a top view of yet a furtherembodiment a lower IC package including a flow barrier.

FIG. 3 is a schematic diagram illustrating a cross-sectional elevationview of an embodiment of a package-on-package (PoP) assembly.

FIG. 4 is a schematic diagram illustrating a cross-sectional elevationview of an embodiment of a computing system including a PoP assembly.

FIG. 5 is a block diagram illustrating embodiments of a method of makinga lower IC package structure, as well as a package-on-package assembly.

DETAILED DESCRIPTION OF THE INVENTION

Disclosed are embodiments of a lower integrated circuit (IC) packagestructure for a package-on-package (PoP) assembly. According to someembodiments, the lower IC package structure includes an interposerhaving pads to couple with mating terminals of an upper IC package. Infurther embodiments, an encapsulant material is disposed in the lower ICpackage, and this encapsulant may be disposed proximate one or more ICdie. In some embodiments, an upper IC package can be coupled with thelower IC package to form a PoP assembly. In other embodiments, such aPoP assembly is disposed on a mainboard or other circuit board, and mayform part of a computing system. Embodiments of a method of making theaforementioned lower IC package, as well as a PoP assembly, are alsodisclosed.

Turning now to FIGS. 1A and 1B, illustrated is an embodiment of a lowerIC package 100. A top view of the lower IC package 100 is shown in FIG.1A, whereas a cross-sectional elevation view, as taken along line B-B ofFIG. 1A, is shown in FIG. 1B. The lower IC package 100 may be coupledwith an upper IC package to form a PoP assembly, and an embodiment ofsuch a PoP assembly will be described in greater detail below (see,e.g., FIG. 3, and the accompanying text).

With continued reference to FIGS. 1A and 1B, the lower IC package 100includes a substrate 110 having a first side 112 and an opposing secondside 114. An IC die 120 is disposed on the first side 112 of substrate110 and is electrically coupled with the substrate by a number ofinterconnects 125. An interposer 130 is also disposed on the substrate'sfirst side 112, and a number of interconnects 140 electrically couple(and perhaps mechanically attach) the interposer 130 to the underlyingsubstrate 110. According to one embodiment, an encapsulant material 150is disposed in the IC package 100, and the encapsulant 150 is positionedproximate the IC die 120. In one embodiment, a layer of an underfillmaterial 160 may be disposed between the IC die 120 and substrate 110.Further, a plurality of electrically conductive terminals 170 (e.g.,lands, solder bumps, metal columns or pillars, etc.) may be disposed onthe second side 114 of substrate 110, and these terminals can be used toform electrical connections with a next-level component, such as amainboard or other circuit board.

Substrate 110—sometimes referred to as a “package substrate”—maycomprise any suitable type of substrate capable of providing electricalcommunications between the IC die 120 and a next-level component towhich the IC package 100 is coupled (e.g., a circuit board). In anotherembodiment, the substrate 110 may comprise any suitable type ofsubstrate capable of providing electrical communication between the ICdie 120 and an upper IC package coupled with the lower IC package, andin a further embodiment the substrate 110 may comprise any suitable typeof substrate capable of providing electrical communication between theupper IC package and a next-level component to which the IC package 100is coupled. The substrate 110 may also provide structural support forthe die 120. By way of example, in one embodiment, substrate 110comprises a multi-layer substrate—including alternating layers of adielectric material and metal—built-up around a core layer (either adielectric or metal core). In another embodiment, the substrate 110comprises a coreless multi-layer substrate. Other types of substratesand substrate materials may also find use with the disclosed embodiments(e.g., ceramics, sapphire, glass, etc.). Further, according to oneembodiment, the substrate 110 may comprise alternating layers ofdielectric material and metal that are built-up over the die 120 itself,this process sometimes referred to as a “bumpless build-up process.”Where such an approach is utilized, the interconnects 125 may not beneeded (as the build-up layers may be disposed directly over the die120).

The IC die 120 may comprise any type of integrated circuit device. Inone embodiment, the IC die 120 includes a processing system (eithersingle core or multi-core). For example, the IC die may comprise amicroprocessor, a graphics processor, a signal processor, a networkprocessor, a chipset, etc. In one embodiment, the IC die 120 comprises asystem-on-chip (SoC) having multiple functional units (e.g., one or moreprocessing units, one or more graphics units, one or more communicationsunits, one or more signal processing units, one or more security units,etc.). However, it should be understood that the disclosed embodimentsare not limited to any particular type or class of IC devices.

The IC die 120 includes a front-side 122 and an opposing back-side 124.In some embodiments, the front-side 122 may be referred to as the“active surface” of the die. A number of interconnects 125 extend fromthe die's front-side 122 to the underlying substrate 110, and theseinterconnects 125 electrically coupled the die and substrate.Interconnects 125 may comprise any type of structure and materialscapable of providing electrical communication between the die 120 andsubstrate 110. According to one embodiment, the interconnects 125comprise an array of solder bumps extending between the die 120 andsubstrate 110 (perhaps in combination with an array of copper columnsand/or copper pads disposed on the die 120 and/or substrate 110), and asolder reflow process may be utilized to form the interconnects 125. Ofcourse, it should be understood that many other types of interconnectsand materials are possible (e.g., wirebonds extending between the die120 and substrate 110). In one embodiment, the interconnects 125electrically coupled the die 120 to substrate 110, and the interconnects125 also aid in mechanically securing the die to the substrate. In afurther embodiment, a layer of underfill material 160 is disposed aroundinterconnects 125 and between the IC die 120 and substrate 110, and thisunderfill layer 160 may also aid in mechanically securing the die 120 tosubstrate 110, as will be described below. Underfill material 160 maycomprise any suitable material, such as a liquid or a pre-applied epoxycompound.

Interposer 130 has a first side 132 and an opposing second side 134,with the second side 134 facing the first side 112 of substrate 110. Inone embodiment, as illustrated in FIGS. 1A-1B, the interposer 130comprises a frame shape having an opening or window 136. Opening 136 mayencompass a periphery 126 of IC die 120; however, in other embodimentsthe opening 136 and die periphery 126 may not be aligned and/or may notbe concentric, and a portion of the die's periphery 126 may extendoutside of the window 136.

It should be understood that the disclosed embodiments are not limitedto a frame-shaped interposer and, further, that interposer 130 may haveany suitable shape and configuration. For example, in anotherembodiment, as shown in FIG. 1C, the interposer 130 comprises a solidrectangular plate without an opening. According to one embodiment, thesolid rectangular plate interposer 130 of FIG. 1C includes a smallaperture 138 for insertion of the encapsulant 150.

Returning to FIGS. 1A and 1B, disposed on the first side 132 ofinterposer 130 is a plurality of electrically conductive terminals 180.Each of the electrically conductive terminals 180 may comprise anysuitable structure and material capable of forming an electricalconnection with a mating terminal of an upper IC package to be joinedwith the lower IC package 100. In one embodiment, each of the terminals180 comprises a pad or land adapted to mate with a correspondingconductive bump extending from the upper IC package, and these matingstructures may be joined by a solder reflow process. However, it shouldbe understood that a terminal 180 may comprise any other type ofstructure (e.g., a column, bump, etc.). Further, in one embodiment, someof the terminals 180 may have a different size and/or structure comparedto other terminals (e.g., terminals used for power delivery may bedifferent than terminals used for signaling, etc.).

As noted above, a number of interconnects 140 extend between theinterposer's second side 134 and the first side 112 of substrate 110,and these interconnects electrically couple the interposer 130—and,hence, an upper IC package coupled to the interposer—with substrate 110.Interconnects 140 may comprise any type of structure and materialscapable of providing electrical communication between the interposer 130and substrate 110. According to one embodiment, the interconnects 140comprise an array of solder bumps extending between the interposer 130and substrate 110 (perhaps in combination with an array of coppercolumns and/or copper pads disposed on the interposer 130 and/orsubstrate 110), and a solder reflow process may be utilized to form theinterconnects 140. Of course, it should be understood that many othertypes of interconnects and materials are possible. In one embodiment,the interconnects 140 also aid in mechanically seeming the interposer130 to the substrate 110. In a further embodiment, as will be describedin greater detail below, the encapsulant material 150 may extend intothe gap 190 between the interposer 130 and substrate 110, and theencapsulant may extend around at least a portion of one or more of theinterconnects 140. Thus, the encapsulant 150 may also aid inmechanically securing the interposer 130 to substrate 110.

As previously noted, an encapsulant 150 is disposed in the IC package100. The encapsulant 150 may comprise any suitable material orcombination of materials. In one embodiment, the encapsulant materialcomprises a liquid epoxy, and in a further embodiment the epoxy includesone or more filler materials to alter one or more characteristics of theepoxy (e.g., curing temperature, hardness, yield strength, modulus ofelasticity, coefficient of thermal expansion, etc.). According to oneembodiment, the encapsulant layer increases the stiffness of the lowerIC package 100 and decreases the package's susceptibility to warpage.For example, during the assembly of lower IC package 100, as well asduring joining with an upper IC package, the IC package 100 may besubjected to multiple high temperature cycles (e.g., during reflow,during epoxy cure, etc.), and this temperature cycling may cause warpage(e.g., due to differential thermal expansion between the die 120 andunderlying substrate 110), and such warpage may lead to reducedreliability and/or structural failure. The increased stiffness providedby encapsulant 150 may alleviate the aforementioned warpage-inducedfailures.

Although referred to herein as an encapsulant, it should be understoodthat this element may be referred to by alternative terminology. Forexample, an encapsulant may be referred to as a mold, molding, overmold,or glob top.

The encapsulant 150 may be placed in the lower IC package 100 at anylocation or locations, as needed, to provide the desired mechanicalcharacteristics for the package assembly. According to one embodiment,as shown in FIGS. 1A and 1B, the encapsulant 150 is disposed over atleast a portion of the back-side 124 of IC die 120, and in someembodiments the encapsulant overlies substantially all of the die'sback-side 124 (see FIG. 1B). In a further embodiment, as also shown inFIGS. 1A and 1B, the encapsulant 150 is disposed over at least a portionof the first side 112 of substrate 110. If an underfill material 160 isdisposed between the IC die 120 and substrate 110, the encapsulant 150may also contact portions of the underfill material (see FIG. 1B). Inone embodiment, as shown in FIG. 1B, the encapsulant extends beyond theperiphery 126 of die 120, but does not extend to regions on substrate110 occupied by interconnects 140. According to one embodiment, as shownin FIG. 1B, the shape of encapsulant 150 is substantially flat above theback-side of die 124 but is rounded near the die's periphery. Also, inone embodiment, as shown in FIG. 1B, the encapsulant 150 does not extendabove the front side 132 of interposer 130, although in the embodimentof FIG. 1B the encapsulant extends above the interposer's second side134 and into the window 136.

It should be understood that FIGS. 1A and 1B illustrate a singleexemplary embodiment of lower IC package 100 and encapsulant 150.However, many other configurations of encapsulant 150 and lower ICpackage 100 are possible. For example, in other embodiments, theencapsulant may not extend into the window 136 and may lie below thesecond side 134 of interposer 130. In a further embodiment, theencapsulant 150 may extend above the interposer's first side 132. Also,the encapsulant may have any other suitable shape and, further, in someembodiments the encapsulant may extend to regions of substrate 110occupied by interconnects 140. Additional embodiments of the lower ICpackage 150 having alternative configurations of encapsulant 150, aswell as additional features, are illustrated in FIGS. 1D through 1L.

Referring first to FIG. 1D, in one embodiment, the encapsulant 150extends above the first side 132 of interposer 130. Also, in theembodiment of FIG. 1D, the encapsulant has a rectangular cross-sectionalprofile with rounded corners. Referring to FIG. 1E, in one embodiment,encapsulant 150 has a shape in which the upper portion is substantiallyrounded. In a further embodiment, as shown in FIG. 1F, the encapsulant150 has a shape that, when viewed in cross-section as shown,approximates a sine wave profile. In the embodiments of FIGS. 1D, 1E,and 1F, the encapsulant is disposed over substantially all of the die'sback-side surface 124 and also contacts underfill material 160. Also, inthe embodiments of FIGS. 1D through 1F, the encapsulant 150 does notextend to locations where interconnects 140 are disposed.

Turning now to FIG. 1G, in one embodiment, the encapsulant extends intothe gap 190 between the interposer 130 and underlying substrate 110.Further, the encapsulant 150 extends into regions occupied byinterconnects 140. In the embodiment of FIG. 1G, the encapsulantsubstantially surrounds one or more of the interconnects 140. In anotherembodiment, as also shown in FIG. 1G, the encapsulant fully fills thegap 190 and extends from the substrate's first surface 112 to theinterposer's second surface 134. However, in other embodiments, theencapsulant may be disposed proximate the interconnects 140 and contactone or more of these interconnects, but may not fully fill the gap 190.Placing encapsulant 150 in the gap 190 between substrate 110 andinterposer 130 and around one or more of the interconnects 140 maystrengthen the mechanical attachment between the interposer 130 andsubstrate 110, as well as increasing the strength and reliability of theelectrical interconnects 140. In the embodiment of FIG. 1G, an upperportion of the encapsulant 150 has a shape approximating a truncatedpyramid (such a shape may be achieved by, for example, a moldingprocess).

In the embodiments shown in FIGS. 1B through 1G, the encapsulant 150 wasdisposed over the back-side 124 of die 120. However, in otherembodiments, the die's back-side 124 may be exposed. For example, asshown in FIG. 1H, the encapsulant 150 contacts the edges of the die'speriphery 126, but the back-side 124 of the die 120 is substantiallyfree of the encapsulant. By way of further example, as shown in FIG. 1I,the encapsulant 150 may extend into gap 190 and around one or moreinterconnects 140, but at least a portion of the die's back-side 124remains substantially free of encapsulant. In the embodiment of FIG. 1I,the encapsulant may extend above the die back-side 124 and onto portionsof this surface proximate the die periphery 126, while other portions ofthe die back-side 124 proximate the center of die 120 remain free ofencapsulant. In one embodiment, exposing at least a portion of theback-side 124 of die 120 may facilitate coupling of coolingsolution—e.g., a layer of thermal interface material, a heat slug, heatspreader, etc. (not shown in figures)—with the die's back-side 124. Inanother embodiment, an exposed portion of die back-side 124 mayfacilitate stacking of one or more additional die on top of die 120,such as die 121 shown in dashed line in each of FIGS. 1H and 1I. Die 121may be coupled with die 120 by any suitable interconnect structure(e.g., thru-silicon vias, or TSVs, wirebonds, etc.).

In the embodiments described thus far, die 120 was coupled withsubstrate 110 by a number of interconnects 125. However, in otherembodiments, alternative structures and/or methods may be utilized tocouple die 120 with substrate 110. For example, as shown in FIG. 1J, thedielectric and metal build-up layers that form substrate 110 may bebuilt up directly over the die 120, in which case a dielectric andsubsequent metal layer may be formed directly on the front-side 122 ofdie 120, with the metal layer forming electrical contact with one ormore bond pads on the die. In such an embodiment, discrete interconnects125 may not be necessary, as metallization in the substrate may directlycontact a die bond pad. Examples of processes that may utilize theaforementioned technique include bumpless build-up layer (BBUL),die-embedding, and wafer-level packaging.

In yet another embodiment, wire bonding may be utilized to electricallycouple the die 120 with substrate 110. With reference to FIG. 1K, thedie 120 may be electrically coupled with substrate 110 by one or morebond wires 127, each bond wire extending between a bond pad on die frontside 122 and a bond pad on substrate 110. Note that in the embodiment ofFIG. 1K, the die 120 has been flipped over with the die back-side 124located adjacent the first side 112 of substrate 110 and perhapsattached to substrate 110 by an adhesive (not shown in figures). In theembodiment of FIG. 1K, the encapsulant 150 extends over the front-sideof die 122, as well as the die's periphery 126, and also over wirebonds127. Also, in this embodiment, the encapsulant 150 has a shape that issubstantially flat above die 120, but the encapsulant is rounded at thedie's periphery 126 and over wirebonds 127.

Turning to FIG. 1L, in another embodiment, two or more die may bedisposed on substrate 110 in a stacked relationship, and wirebonds maybe used to form electrical connections between each of these die and/orwith substrate 110. By way of example, as shown in FIG. 1L, three die120 a, 120 b, 120 c may be arranged in a stack and disposed on the firstside 112 of substrate 110. One or more wirebonds 127 may electricallycouple each of the die 120 a, 120 b, 120 c to any one or more of theother die and/or with substrate 110. In the embodiment of FIG. 1L, theencapsulant 150 extends through window 136 of interposer 130 and abovethe interposer's first surface 132. Further, the encapsulant extendsinto the gap 190 between the interposer 130 and substrate 110, as wellas around one or more of the interconnects 140.

As described above, in some embodiments, the encapsulant 150 may notextend into regions of the lower IC package 100 where interconnects 140are disposed. According to one embodiment, where it is desired toprevent flow of encapsulant into regions where interconnects 140 arelocated (or to any other region of the lower IC package 100), one ormore flow barriers or other flow control devices or structures may beutilized to control the flow of encapsulant 150 within IC package 100.Any suitable flow barrier, or combination of barriers, may be utilizedto control flow of encapsulant 150, such as dams, non-wetting coatings,and trenches, as well as any suitable combination of these and/or otherfeatures. Various exemplary embodiments of flow barriers are illustratedin FIGS. 2A through 2E.

Referring to FIG. 2A, in one embodiment, a dam 205 a is disposed on thefirst surface 112 of substrate 110. The dam 205 a may be disposed at anysuitable location (or locations) in lower IC package 100, as desired, toinhibit the flow of encapsulant 150. In the embodiment of FIG. 2A, forexample, the dam 205 a is positioned between the periphery 126 of IC die120 and the set of interconnects 140. Thus, the dam 205 a inhibits theflow of encapsulant 150 into regions of IC package 100 occupied byinterconnects 140. The dam 205 may be constructed from any suitablematerials (e.g., metals, polymers, composites, etc.), and may be bondedto the substrate 110 by any suitable technique (e.g., by an adhesive, byreflowed solder, by diffusion bonding, etc.). In another embodiment, thedam 205 a is coupled with the interposer 130 rather than substrate 110,and in a further embodiment the dam 205 a is coupled with both thesubstrate 110 and interposer 130. According to another embodiment, thedam 205 a is formed integral with the substrate 110 (or, alternatively,is formed integral with interposer 130).

Referring next to FIG. 2B, in another embodiment, a non-wetting coatingor layer 205 b is disposed on the substrate's first surface 112, whereinthe non-wetting layer comprises a material that is non-wetting withrespect to the encapsulant material 150. The non-wetting layer 205 b maybe disposed at any suitable location (or locations) in lower IC package100, as desired to inhibit the flow of encapsulant 150. In oneembodiment, the non-wetting layer 205 b is positioned between theperiphery 126 of IC die 120 and the array of interconnects 140 and,therefore, the non-wetting layer 205 b inhibits the flow of encapsulant150 into regions of IC package 100 occupied by interconnects 140. Thenon-wetting layer 205 b may comprise any suitable material orcombination of materials that is non-wetting with respect to theencapsulant material 150 (e.g., fluoropolymers, etc.), and may bedisposed on the substrate 110 by any suitable technique (e.g., byspray-coating using a mask, by photolithography, by dispensing using aneedle or syringe, etc.). In another embodiment, the non-wetting layer205 b is disposed on the interposer 130 rather than substrate 110, andin a further embodiment a non-wetting layer 205 b is disposed on each ofthe substrate 110 and interposer 130.

Turning to FIG. 2C, in a further embodiment, a trench 205 c is disposedon the first surface 112 of substrate 110. The trench 205 c may bedisposed at any suitable location (or locations) in lower IC package100, as desired to inhibit the flow of encapsulant 150. In theembodiment of FIG. 2C, for example, the trench 205 c is positionedbetween the periphery 126 of IC die 120 and the set of interconnects 140and, accordingly, the trench 205 c inhibits the flow of encapsulant 150into regions of IC package 100 occupied by the interconnects 140. Thetrench 205 c may be formed using any suitable technique (e.g., byetching, by machining, by laser ablation, etc.). In another embodiment,a trench 205 c is disposed on the interposer 130 rather than substrate110, and in a further embodiment a trench 205 c is formed on each ofsubstrate 110 and interposer 130.

In one embodiment, a flow barrier or structure may extend around aperiphery of the die 120 and through the region between the die 120 andinterconnects 140. For example, in one embodiment, as shown in FIG. 2D,a barrier (e.g., 205 a, or 205 b, or 205 c) is disposed on the firstsurface 112 of substrate 110, and is positioned on the substrate firstsurface 112 between the die 120 and a region 145 occupied byinterconnects 140. According to one embodiment, the flow barrier (205 a,or 205 b, or 205 c) extends entirely around the die's periphery 126;however, in other embodiments, a flow barrier may be discontinuous andone or more breaks or voids may exist in this structure. By way ofexample, in one embodiment, as shown in FIG. 2E, a flow barrier (e.g.,205 a, or 205 b, or 205 c) may comprises a plurality of separatediscrete elements that, together, inhibit the flow of encapsulant 150.In yet a further embodiment, a flow barrier may comprise a plurality ofdiscrete elements disposed on the substrate 110 (or interposer 130), andthese discrete elements may comprise passive electrical devices (e.g., acapacitor, resistor, inductor, or any combination of these and/or otherdevices).

Referring now to FIG. 3, illustrated is an embodiment of apackage-on-package (PoP) assembly 302. The PoP assembly 302 includes alower IC package 100 and an upper IC package 300. Lower IC package 100may comprise any one of the embodiments of a lower IC package describedherein. According to one embodiment, lower IC package 100 includes oneor more processing systems and upper IC package 300 includes one or morememory devices. In another embodiment, lower IC package 100 includes oneor more processing systems and upper IC package 300 comprises a wirelesscommunications system (or, alternatively, includes one or morecomponents of a communications system). In a further embodiment, lowerIC package 100 includes one or more processing systems and upper ICpackage 300 includes a graphics processing system. The PoP assembly 302may comprise part of any type of computing system, such as a hand-heldcomputing system (e.g., a cell phone, smart phone, music player, etc.),mobile computing system (e.g., a laptop, nettop, tablet, etc.), adesktop computing system, or a server. In one embodiment, the PoPassembly comprises a solid state drive (SSD).

Upper IC package 300 may comprise any suitable package structure. In oneembodiment, as shown in FIG. 3, the upper IC package 300 comprises anumber of IC die 320 a, 320 b, 320 c disposed on a package substrate310. A number of wirebonds 327 electrically connect each of the die 320a, 320 b, 320 c with one or more of the other die and/or with substrate310. A molding material 355 may be disposed over the die 320 a-c andsubstrate 310. According to one embodiment, a plurality of interconnects340 couple the upper IC package 300 to lower IC package 100. In oneembodiment, the set of interconnects 340 are coupled with the set ofterminals 180 on the interposer 130.

Each of the interconnects 340 may comprise any type of structure andmaterials capable of providing electrical communication between theupper and lower IC packages 100, 300. According to one embodiment, theset of interconnects 340 comprises an array of solder bumps extendingbetween bond pads 180 on the interposer 130 of lower IC package 100 andthe substrate 310 of upper IC package 300 (perhaps in combination withan array of columns and/or pads disposed on the substrate 310). A solderreflow process may be utilized to form the plurality interconnects 340.Of course, it should be understood that many other types ofinterconnects and materials are possible. In one embodiment, the arrayof interconnects 340 also aid in mechanically securing the upper ICpackage 300 to the lower IC package 100.

In one embodiment, as illustrated in FIG. 3, a gap 395 may exist betweenan upper surface of encapsulant 150 and a lower surface of substrate310. In another embodiment, the substrate 310 may rest upon theencapsulant 150. Where the substrate 310 contacts the encapsulant 150,the encapsulant may be utilized to control the stand-off height betweenthe interposer 130 and substrate 310 and, hence, to maintain a desiredheight of interconnects 340.

Turning now to FIG. 4, illustrated is an embodiment of a computingsystem 400. The system 400 includes a number of components disposed on amainboard 410 or other circuit board. Mainboard 410 includes a firstside 412 and an opposing second side 414, and various components may bedisposed on either one or both of the first and second sides 412, 414.In the illustrated embodiment, the computing system 400 includes a PoPassembly 302 disposed on the mainboard's first side 412, and PoPassembly 302 may comprise any of the embodiments described herein.System 400 may comprise any type of computing system, such as ahand-held computing device (e.g., a cell phone, a smart phone, a mobileinternet device, a music player, etc.) or a mobile computing device(e.g., a laptop computer, a nettop computer, tablet computer, etc.).However, the disclosed embodiments are not limited to hand-held andother mobile computing devices and these embodiments may findapplication in other types of computing systems, such as desk-topcomputers and servers.

Mainboard 410 may comprise any suitable type of circuit board or othersubstrate capable of providing electrical communication between one ormore of the various components disposed on the board. In one embodiment,for example, the mainboard 410 comprises a printed circuit board (PCB)comprising multiple metal layers separated from one another by a layerof dielectric material and interconnected by electrically conductivevias. Any one or more of the metal layers may be formed in a desiredcircuit pattern to route—perhaps in conjunction with other metallayers—electrical signals between the components coupled with the board410. However, it should be understood that the disclosed embodiments arenot limited to the above-described PCB and, further, that mainboard 410may comprise any other suitable substrate.

As noted above, disposed on the first side 412 of mainboard 410 is a PoPassembly 302. The PoP assembly 302 may comprise an upper IC package 300coupled with a lower IC package 100, as previously described. The PoPassembly 302 may include any desired combination of integrated circuitdevices. In one embodiment, the PoP assembly 302 includes any one ormore of a processing system, a graphics processing system, a signalprocessing system, a wireless communications system, a networkprocessing system, a chipset, a memory, as well as combinations of theseand/or other systems. In one embodiment, an IC die disposed in PoPassembly 302 comprises a system-on-chip (SoC). However, it should beunderstood that the disclosed embodiments are not limited to anyparticular type or class of IC devices. Also, it should be noted that,in some embodiments, other components may be disposed oil the PoPassembly 302. Other components that may be disposed in PoP assembly 302include, for example, a voltage regulator and passive electricaldevices, such as capacitors, resistors, filters, inductors, etc.

The PoP assembly 302 is electrically connected with mainboard 410 by aplurality of terminals 170 (e.g., lands, solder bumps, metal columns orpillars, etc.) extending from the PoP assembly, which are coupled withcorresponding terminals (e.g., bond pads, bumps, columns, pillars, etc.)on the substrate 410. Any suitable process may be utilized to formelectrical connections between the set of terminals 170 of PoP assembly302 and the corresponding set of terminals on substrate 410. Forexample, these mating terminals may be electrically coupled (and perhapsmechanically joined) by a solder reflow process.

In addition to PoP assembly 302, one or more additional components maybe disposed on either one or both sides 412, 414 of the mainboard 410.By way of example, as shown in the figures, components 401 a may bedisposed on the first side 412 of the mainboard 110, and components 401b may be disposed on the mainboard's opposing side 414. Additionalcomponents that may be disposed on the mainboard 410 include other ICdevices (e.g., processing devices, memory devices, signal processingdevices, wireless communication devices, etc.), power deliverycomponents (e.g., a voltage regulator, a power supply such as a battery,and/or passive devices such as a capacitor), and one or more userinterface devices (e.g., an audio input device, an audio output device,a keypad or other data entry device such as a touch screen display,and/or a graphics display, etc.), as well as any combination of theseand/or other devices. In another embodiment, the computing system 400includes a radiation shield. In a further embodiment, the computingsystem 400 includes a cooling solution. In yet another embodiment, thecomputing system 400 includes an antenna. In yet a further embodiment,the assembly 400 may be disposed within a housing.

Referring to FIG. 5, illustrated are embodiments of a method of making alower IC package, as well as attaching the lower IC package to an upperIC package to form a PoP assembly. As set forth in block 510, one ormore IC die are attached to a substrate, and in some embodiments anunderfill material may be disposed between an IC die and the substrate(see, e.g., die 120—or 120 a-c—and underfill 160 in any of theembodiments illustrated in FIGS. 1A through 1L, as well as theaccompanying text above). As set forth in block 520, an interposer iscoupled with the substrate (see, e.g., interposer 130 in any of theembodiments of FIGS. 1A through 1L). As set forth in block 530, anencapsulant is disposed in the lower IC package (see, e.g., encapsulant150 in any of the embodiments of FIGS. 1A through 1L). The encapsulant150 may be disposed in the IC package using any suitable technique, suchas by a syringe or needle dispenser, by molding, by stencil printing,etc. In one embodiment, as set forth in block 515, one or more flowbarriers are disposed in the lower IC package to control flow ofencapsulant 150 (see, e.g., flow barriers 205 a-c in any of theembodiments illustrated in FIGS. 2A through 2E, as well as theaccompanying text above). According to one embodiment, the substrate andinterposer are constructed as part of a panel or strip, and one or moreof the aforementioned assembly processes may be performed at the panellevel, in which case the discrete package assemblies are separated fromone another by a singulation process, as set forth in block 535. In yetanother embodiment, as set forth in block 540, an upper IC package isattached to the lower IC package to form a PoP assembly (see, e.g., FIG.3 and the accompanying text above).

Numerous embodiments have been described with respect to FIGS. 1A though1L, FIGS. 2A through 2E, FIG. 3, FIG. 4, and FIG. 5, and it should beunderstood that these embodiments, or certain features of an embodiment,may be used in any combination. For example, any of the flow barriersillustrated in FIGS. 2A through 2E may be utilized with any of the otherembodiments described herein. By way of further example, any of theembodiments of a lower IC package illustrated in FIGS. 1A through 1L mayform part of a PoP assembly (e.g., see FIG. 3) or a computing system(e.g., see FIG. 4). Also, terms such as “first side”, “second side”,“first surface”, “second surface”, and so on, are used herein todescribe various features of the disclosed embodiments. However, itshould be understood that any suitable nomenclature or terminology maybe ascribed to the various features and embodiments disclosed herein(e.g., “upper side”, “lower side”, “upper surface”, “lower surface”,etc.).

The above-described embodiments may exhibit several noteworthy features.The combination of the interposer and encapsulant can reduce packagewarpage during temperature cycling (e.g., at reflow temperatures), andcan also reduce package warpage of the final assembly (e.g., at roomtemperature). Simulation studies have suggested that the combination ofthe interposer and encapsulant can, in some embodiments, potentiallyreduce by over half the warpage that occurs during temperature cyclingand, further, reduce by over half the warpage of the final assembly. Inaddition, the interposer may provide pads to mate with bumps (or otherterminals) extending from the upper IC package, which eliminates a bumptip-to-bump tip interface that can occur where interconnects between theupper and lower IC packages comprise a bump-on-bump structure.Eliminating such bump tip-to-bump tip engagements during assembly canminimize misalignment between the upper and lower IC packages and,further, may reduce non-wet solder joint failures. Also, a solderbumping step is not needed on the interposer prior to attachment to theupper IC package (however, application of a solder paste layer to padson the interposer is within the scope of the disclosed embodiments).Furthermore, in addition to providing increased package stiffness, theencapsulant can protect any IC die disposed in the lower IC package andreduce die cracking. In some embodiments, a thin die (e.g., a die havinga thickness of 250 micrometers, or less) may be disposed in the lower ICpackage, and the encapsulant can protect such a thin die.

The foregoing detailed description and accompanying drawings are onlyillustrative and not restrictive. The figures may not show the actualsize and/or scale of features that are represented. The figures havebeen provided primarily for a clear and comprehensive understanding ofthe disclosed embodiments and no unnecessary limitations are to beunderstood therefrom. Numerous additions, deletions, and modificationsto the embodiments described herein, as well as alternativearrangements, may be devised by those skilled in the art withoutdeparting from the spirit of the disclosed embodiments and the scope ofthe appended claims.

1. A lower integrated circuit (IC) package, the lower IC package forcoupling with an upper IC package to form a package-on-package assembly,the lower IC package comprising: a substrate having a first side and anopposing second side; an IC die coupled with the first side of thesubstrate; an encapsulant, the encapsulant disposed over at least aportion of a surface of the die and over at least a portion of the firstside of the substrate; an interposer having a first side and an opposingsecond side, the second side of the interposer facing the first side ofthe substrate; a number of interconnects electrically coupling theinterposer with the substrate; and a plurality of terminals disposed onthe first side of the interposer, the plurality of terminals for formingelectrical connections with the upper IC package.
 2. The lower ICpackage of claim 1, further comprising a barrier to control flow of theencapsulant.
 3. The lower IC package of claim 2, wherein the barrierinhibits flow of the encapsulant toward the number of interconnects. 4.The lower IC package of claim 2, wherein the bather comprises astructure selected from a group consisting of a dam, a coating that isnon-wetting with respect to the encapsulant, and a trench.
 5. The lowerIC package of claim 1, wherein a portion of the surface of the IC die issubstantially free of encapsulant.
 6. The lower IC package of claim 1,wherein the encapsulant extends over at least a portion of a surface ofone or more of the number of interconnects.
 7. The lower IC package ofclaim 6, wherein the encapsulant substantially surrounds all of theinterconnects.
 8. The lower IC package of claim 1, wherein theinterposer comprises a frame having an opening.
 9. The lower IC packageof claim 8, wherein the encapsulant extend into the opening.
 10. Thelower IC package of claim 9, wherein the encapsulant extends above thefirst side of the interposer.
 11. The lower IC package of claim 1,further comprising an underfill material disposed between the IC die andthe first side of the substrate, wherein the encapsulant contacts atleast a portion of the underfill material.
 12. The lower IC package ofclaim 1, further comprising a number of wirebonds electrically couplingthe IC die with the substrate, wherein the encapsulant is disposed overat least one of the wirebonds.
 13. The lower IC package of claim 1,wherein the substrate is built up directly over the IC die.
 14. Thelower IC package of claim 1, wherein at least one of the plurality ofterminals comprises an electrically conductive pad, the pad capable offorming an electrical connection with a metal bump extending from theupper IC package.
 15. The lower IC package of claim 1, furthercomprising a second plurality of terminals disposed on the second sideof the substrate, the second plurality of terminal for electricallycoupling the lower IC package with a circuit board.
 16. The lower ICpackage of claim 1, further comprising at least one other IC die stackedover the IC die, wherein the encapsulant is disposed over at least aportion of a surface of the at least one other IC die.
 17. Apackage-on-package (PoP) assembly comprising: a lower integrated circuit(IC) package, the lower IC package including a substrate having a firstside and an opposing second side, an IC die coupled with the first sideof the substrate, an interposer having a first side and an opposingsecond side that faces the first side of the substrate, a number ofinterconnects electrically coupling the interposer with the substrate,and an encapsulant, the encapsulant disposed over at least a portion ofa surface of the die and over at least a portion of the first side ofthe substrate; an upper IC package; and a plurality of interconnectselectrically coupling the upper IC package with the first side of theinterposer.
 18. The PoP assembly of claim 17, wherein the upper ICpackage comprises at least one IC die disposed on a second substrate.19. The PoP assembly of claim 18, further comprising: an electricallyconductive pad disposed on the first side of the interposer; wherein atleast one of the plurality of interconnects includes a solder bumpextending from the second substrate and coupled with the conductive pad.20. The PoP assembly of claim 17, further comprising a barrier disposedin the lower IC package to control flow of the encapsulant.
 21. The PoPassembly of claim 20, wherein the barrier inhibits flow of theencapsulant toward the number of interconnects.
 22. The PoP assembly ofclaim 20, wherein the barrier comprises a structure selected from agroup consisting of a dam, a coating that is non-wetting with respect tothe encapsulant, and a trench.
 23. The PoP assembly of claim 17, whereinthe encapsulant extends over at least a portion of a surface of one ormore of the number of interconnects.
 24. The PoP assembly of claim 23,wherein the encapsulant substantially surrounds all of the number ofinterconnects.
 25. The PoP assembly of claim 17, wherein the interposercomprises a frame having an opening.
 26. The PoP assembly of claim 25,wherein the encapsulant extend into the opening.
 27. The PoP assembly ofclaim 26, wherein the encapsulant extends above the first side of theinterposer.
 28. The PoP assembly of claim 17, wherein the substrate ofthe lower IC package is built up directly over the IC die.
 29. The PoPassembly of claim 17, further comprising a plurality of terminals on thesecond side of the substrate of the lower IC package, the plurality ofterminals for electrically coupling the PoP assembly with a circuitboard.
 30. The PoP assembly of claim 17, further comprising at least oneother IC die stacked over the IC die of the lower IC package, whereinthe encapsulant is disposed over at least a portion of a surface of theat least one other IC die.
 31. A computing system comprising: amainboard; a package-on-package (PoP) assembly disposed on themainboard, the PoP assembly including a lower IC package, an upper ICpackage, and a plurality of interconnects electrically coupling theupper IC package with the lower IC package; a processing system disposedin the PoP assembly; and at least one user interface device disposed onthe mainboard; wherein the lower IC package comprises a substrate havinga first side and an opposing second side, an IC die coupled with thefirst side of the substrate, an interposer having a first side and anopposing second side that faces the first side of the substrate, anumber of interconnects electrically coupling the interposer with thesubstrate, and an encapsulant, the encapsulant disposed over at least aportion of a surface of the die and over at least a portion of the firstside of the substrate; and wherein the plurality of interconnects extendbetween the first side of the interposer and the upper IC package. 32.The computing system of claim 31, wherein the IC die of the lower ICpackage includes the processing system.
 33. The computing system ofclaim 32, further comprising a memory disposed in the upper IC packageof the PoP assembly.
 34. The computing system of claim 31, wherein thePoP assembly includes at least part of a communications system.
 35. Thecomputing system of claim 31, wherein the user interface devicecomprises a device selected from a group consisting of an audio inputdevice, an audio output device, a keypad, a touch screen, and a graphicsdisplay.
 36. The computing system of claim 31, further comprising atleast one component selected from a group consisting of an antenna, apower supply, an IC device, a voltage regulator, a radiation shield, acooling device, and a passive electrical device.